RISC-V: Unveiling the Potential of Open-Source ISA

RISC-V, an open ISA based on RISC principles, originated at UC Berkeley around 2010 and was standardized in 2013. It gained traction as an alternative to proprietary ISAs like ARM or x86 due to its open-source nature and customizable features. Its configurability and modularity have fueled its rapid adoption, allowing vendors to tailor processors for various workloads. InCore leverages this modularity to design highly configurable processors, offering tailored instances for specific RISC-V subsets. With its open-source, scalable architecture, RISC-V provides significant advantages for developers, making it an exciting technology for the future. Learn more at riscv.org.

Explore our RISC-V Offerings

Core-hub Generators: Streamlining Custom Processor Design

What makes us different: Automated design flow

SaaS agility to hardware

Leveraging CI/CD methodologies, hardware engineering undergoes a transformative shift, akin to SaaS development agility. It enables seamless integration of iterative changes and automated testing, fostering rapid prototyping, collaboration, and scaling. This streamlines the hardware development process, reducing time-to-market, fostering innovation, and ensuring high-quality, reliable products at scale.

Parametrized Libraries

The BSV advanced HL-HDL pioneers a methodology prioritizing correctness through construction, reducing bugs and setting new standards in quality. It ensures higher efficiency and reliability in hardware design, thereby reducing  the design cycle time for complex SoC designs.

Automated verification

We ease verification with automated generators, ensuring comprehensive testing, corner case coverage and guaranteeing ISA/uARCH compliance. Continuous integration and regression testing ensures high minimum verification standards.

YAML to all things silicon

All our code, verification suites and documentation are generated from a single YAML source. This ensures our code, verification suite and documentation are always in sync with each other.

Pre-defined templates

We simplify custom hardware development with pre-defined SoC templates that are aligned with market trends and requirements.

FPGA flows

We streamline FPGA prototyping on platforms like Xilinx, enabling instant setup for firmware and software teams, enhancing collaboration and productivity for success.

ASIC flows

We accelerate ASIC flows, allowing PPA targets to be met rapidly leading to significant reduction in design cycles.

Doc Generator: Streamlining Documentation for Core Instances

Our Doc Generator uses  the same YAML spec used to generate our Core-hubs. This ensures that the documentation is never out of sync with the code.

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