The FlexiCore Techonology

The Power of Core-Hub Generators

InCore’s RISC-V Core-Hub Generators are software tools that generate hardware designs based on proprietary RISC-V processors. These generators provide a quick and efficient way to create customized processor cores that meet specific requirements. They enable developers to configure the processor's microarchitecture to meet specific application needs, which is an extension of the RISC-V’s philosophy of configurable and modular architecture is essential in today's rapidly changing computing landscape.

The RISC-V ISA is designed to be configurable, scalable, and extensible. The instruction set is divided into a base set of instructions, which are required for all RISC-V implementations, and a set of optional extensions that can be added as per application requirements. These extensions enable the processor to perform specific tasks more efficiently and effectively, such as vector processing, cryptography, or floating-point arithmetic. Similarly, RISC-V core generators provide a flexible and customizable way to create processor cores that match the specific needs of a particular application. They allow developers to add or remove features such as pipeline stages, caches, and ports to optimize performance, reduce power consumption, and minimize area.

In addition to flexibility and configurability, RISC-V core generators provide a high-level of abstraction, enabling developers to focus on the application-level requirements rather than the hardware details. This abstraction also makes it easier to generate processor cores that meet design constraints such as area, power, and performance.

BSV: The Spine

YAML: The Config Lang

The RISC-V Core-Hub Generators at InCore are designed using Bluespec System Verilog (BSV). BSV is a high-level hardware description language that is becoming increasingly popular for building highly parameterized designs because of its modular and scalable approach to hardware design, enabling developers to create complex and customizable designs quickly and efficiently. Apart from guaranteeing fully synthesizable designs, one of the key advantages of using BSV for parameterized design is the language's built-in support for parameterization and for type-safe, compositional design methodology. BSV modules are designed to be composable, enabling developers to build complex designs from smaller, reusable modules. This compositional approach helps to simplify design and verification tasks by promoting a modular and hierarchical design methodology. While the base processor pipeline configuration for each Core-Hub Generator is frozen, almost all other components of the processor are designed as customizable hardware add-ons to allow exploration quickly and efficiently, thereby making BSV an excellent choice for a wide range of embedded and high-performance computing systems.
The RISC-V Core-Hub Generators use YAML to capture the core configuration which can then be further optimized. YAML is a human-readable and intuitive language for capturing configuration and data. Its syntax is simple and easy to understand and uses indentation to indicate structure, making it easy to read and write. The different layers of configurations - ISA and Microarchitecture (uArch) - are split into multiple YAML inputs to the Core-Hub Generators .

The ISA configurations are captured using RISCV-CONFIG, an InCore donated Specification Validator, which allows the user to capture all privileged and unprivileged aspects of the core (including specifying custom WARL behaviors for CSRs)

The uArch configurations are captured in a similar YAML style with inhouse schemas which control the various features of the processors which are agnostic of the ISA, like cache sizes, branch predictors, multiplication latency, csrs-daisy chain, etc. The combination of ISA and uArch configurations allows each Core-Hub Generator to span an extensive design space and produce highly fine-tuned and optimized RISC-V Cores for an application.

Verification Generators

Verification is a critical step in the design process, and it becomes even more important as the design complexity increases. RISC-V core generators can indeed accelerate the design creation process, but scaling the verification process can be challenging. At InCore, we recognize the importance of verification, and our cutting-edge methodology reimagines the verification process to scale with the design complexity. Our verification generators automate much of the verification process, reducing bugs and simplifying the verification process.

Automated Test Generation

InCore employs Automated test generation tools to create a wide range of test scenarios for the generated cores. These tests will cover various corner cases, ensuring that the core behaves as expected under diverse conditions. The test generators themselves are tuned and designed to attack specific layers of processor verification: ISA compliance, uArch Compliance and Random Testing

Continuous Integration and Regression Testing

InCore implements a continuous integration (CI) system thus, ensuring that the core generator's code is consistently tested and verified. Regular regression testing is used to catch any issues introduced by changes in the code, ensuring the generator remains functional and accurate.

Standardized Test Suites and Compliance

Utilizing standardized test suites and compliance tests(Authored and Maintained by InCore), such as those provided by the RISC-V Foundation, helps ensure that the generated cores are compatible with the broader RISC-V ecosystem.

By implementing these verification methods and leveraging scalable verification infrastructures, RISC-V core generators can be effectively and efficiently verified, ensuring reliable, high-quality processor cores.

Doc Generator

When using RISC-V core generators, it's crucial to have accurate documentation corresponding to each generated processor core instance. A Doc generator running in tandem with`the core generator ensures that documentation matches the specific instance created.

A document generator automatically extracts relevant information from the core generator's output, such as configuration details, architecture, and features. This information is compiled into a comprehensive reference focus.