The RISC-V Core-Hub Generators at InCore are designed using Bluespec System Verilog (BSV). BSV is a high-level hardware description language that is becoming increasingly popular for building highly parameterized designs because of its modular and scalable approach to hardware design, enabling developers to create complex and customizable designs quickly and efficiently. Apart from guaranteeing fully synthesizable designs, one of the key advantages of using BSV for parameterized design is the language's built-in support for parameterization and for type-safe, compositional design methodology. BSV modules are designed to be composable, enabling developers to build complex designs from smaller, reusable modules. This compositional approach helps to simplify design and verification tasks by promoting a modular and hierarchical design methodology. While the base processor pipeline configuration for each Core-Hub Generator is frozen, almost all other components of the processor are designed as customizable hardware add-ons to allow exploration quickly and efficiently, thereby making BSV an excellent choice for a wide range of embedded and high-performance computing systems.
The RISC-V Core-Hub Generators use YAML to capture the core configuration which can then be further optimized. YAML is a human-readable and intuitive language for capturing configuration and data. Its syntax is simple and easy to understand and uses indentation to indicate structure, making it easy to read and write. The different layers of configurations - ISA and Microarchitecture (uArch) - are split into multiple YAML inputs to the Core-Hub Generators .
The ISA configurations are captured using RISCV-CONFIG, an InCore donated Specification Validator, which allows the user to capture all privileged and unprivileged aspects of the core (including specifying custom WARL behaviors for CSRs)
The uArch configurations are captured in a similar YAML style with inhouse schemas which control the various features of the processors which are agnostic of the ISA, like cache sizes, branch predictors, multiplication latency, csrs-daisy chain, etc. The combination of ISA and uArch configurations allows each Core-Hub Generator to span an extensive design space and produce highly fine-tuned and optimized RISC-V Cores for an application.