Its 2025, chip design doesn't have to be difficult! Transform your workflow with automated SOC design
Overview
How it works
Simple editable SoC specs serve as a central source of info for the entire flow.
Automation to reduce redundancy, minimize human error, and ensure consistency in SoC development
The outputs address 4 key areas of SoC development: Hardware, Verification, Software & Documentation
SoC-gen output
Get your SOC-subsystem on Day 1
SoC Subsystem RTL
Connectivity
RISC-V Cores
AXLs
UnCore
NoC
Peripheral IPs
- GCC GNU Toolchain
- LLVM Toolchain
- GBD
- OpenOCD
- ISA Models
- SW Dev Kit (SDK)
- Integrated Dev Env
- Standard OS BSPs
Software
- eUVM based Flow
- Unit Level NoC Tests
- ASM Tests for Cores
- SoC Integration Tests
- Standalone IP Tests
- RDL, UVM, IPXACT Models
Verification
- Ready2Use Ref-SoC
- Xilink Board IP
- Extendable SoCs
FPGA
- Constraints
- Lint Scripts
- Synth Scripts
ASIC
One tool, many benefits
How it helps different teamsÂ
Hardware Design
Team
Team
Documentation Team
Verification Team
System Architecture Team
FPGA
Prototyping Team
Prototyping Team
Project Management Team
Hardware Design Team
Verification Team
FPGA Prototyping Team
Documentation Team
System Architecture Team
Project Management Team
Business impact
Reduce $$, time, risk of new SoC design startsÂ
Seamless Transition to a RISC-V SoC
Streamline IP Management
A wingman for Frontend Engineers
SoC-gen case study
Below is a secure SoC subsystem built by the tool in minutes
Features
- AES accelerator with support for various modes
- SHA accelerator (256/512) with performance or area optimised variants
- Big number accelerator for RSA and ECC algorithms
- Secret Keystore: secret keys cannot be leaked by any agent including the processor
- Secure Memory module to store user data in a secure manner
- Worldguard based trusted execution environment
- Secure Boot framework: elf signing, key management and boot code using security accelerators
- Standard RISC-V security features: privilege modes (M,S,U,HS,VS,VU) and PMPs
- Secure debug module
- On-the-fly memory encryption of all code and data between processor and memory
Bring your own IP
How we do it
- Automated wrapper construction for your IP (the largest IP wrapper takes 3-4 days + 1 day for RTL collateral integration).
- Python plugin for the IP to work with the generator.
sales enquiry
For more contact info visit here.
