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RISC-V Memory Protection: Diving Deep into the Complexities
Prologue RISC-V is an open and modular architecture that enables customizable and efficient processor designs. When secure processing is of interest, it is necessary to understand the memory protection mechanisms that are part of the architecture. RISC-V supports an optional physical memory protection (PMP) unit, designed to protect machine secrets, that provides per-hart memory protection…
A Compelling Case for Using BSV (Bluespec System Verilog) in Academia: Insights from Redesigning a Capstone Project
Introduction At InCore, the use of Bluespec SystemVerilog (BSV) is one of the superpowers that enables small teams like ours to specify complex hardware intuitively and efficiently. Like most undergraduate students, I started out designing digital logic in Verilog, with reference to coding guidelines from professors, coursework, and literature. Back then, specifying designs dealing with parallelism…
The Age of Custom Silicon
With industry titans like Nvidia, Intel and ARM jumping on the bandwagon of custom silicon, it can be safely concluded that the age of custom silicon is well upon us. This has interesting repercussions for the semicon industry and changes how chips are designed and sold. The clear winners are the foundries. Other players like…
Challenges with Open Source RISC-V Cores
From Academia to Industry: Lessons from SHAKTI SHAKTI is a project I hold dear, having been there from its inception. But as with any journey from the lab to the market, there are some interesting challenges we encountered. I'd like to share these constructive insights, as valuable lessons that have shaped our approach at InCore.…
SHAKTI’s Genesis
Discover the journey of RISC-V in India, from the SHAKTI program at IIT Madras to InCore Semiconductors. Explore key milestones and achievements in open-source processor design, highlighting India's innovation and self-reliance in technology.
Our Recommendations
RISC-V Memory Protection: Diving Deep into the Complexities
A Compelling Case for Using BSV (Bluespec System Verilog) in Academia: Insights from Redesigning a Capstone Project
The Age of Custom Silicon
Challenges with Open Source RISC-V Cores